A computing system is typically designed to store software instructions and data within the computing system's system memory. Typically there is a noticeable latency or delay associated with the storing of data into system memory and the fetching of instructions and data from the system memory. As such, in an attempt to avoid these delays/latencies where possible, many computing systems also include a cache.
A cache is a storage resource that, from the perspective of the central processing unit (CPU), has a noticeably smaller associated latency than system memory (e.g., by being located closer to the CPU than the system memory and/or being constructed with faster storage cells). Generally, the computing system attempts to store frequently used data and instructions into the cache. By storing frequently used data and instructions in the cache the average latency associated with the storage of data and/or the fetching of data and instructions is noticeably less than the latency of system memory. This reduction in average latency translates into an improvement in the performance of the computing system.
Items of data or instructions are typically stored in the cache along with their associated system memory address. If a CPU needs a particular data item or instruction item the CPU identifies it through its system memory address. The cache is then searched for the data/instruction item by searching through the addresses of the items stored within the cache. If the address of a stored item matches the address of the requested item, the cache is understood to contain the desired item (“a hit”). The item is then delivered to the CPU from the cache thereby avoiding the additional delay associated with accesses made to the system memory.
Many cache architectures are organized to partition their storage resources according to the addresses of the data/instruction items that may be stored (and searched for) in the cache. In a particular approach, the storage resources of the cache are divided into sets where each set has a plurality of storage locations referred to as ways. According to one cache search approach, a particular address that is presented to the cache for searching (a “search address”) is viewed as having both a set component and a tag component. For the given search address, an appropriate set is identified based on the search address's set component. The tag component of the search address is them compared against the respective tag components of the addresses of the cached items within the ways of the set. A match corresponds to a cache hit.
FIG. 1 shows a typical circuit for performing such a cache search. The respective tag components 101_1, 101_2 of items cached in the respective ways of the set 102 are stored along with their own associated error correction codes (ECC) 102_1, 102_2. According to the operation of the circuit of FIG. 1, the tags of two cached items and their associated ECC codes are read from the cache substantially simultaneously. ECC checking and correction circuitry 103_1, 103_2 generates a second ECC for each tag, and, if the newly generated ECC is different than the stored ECC for the respective tag an error in the tag value is flagged and corrected.
The correct tags are then compared against the tag component 104 of the search address by respective comparison circuits 105_1, 105_2. A match found by either of the comparison circuits corresponds to a cache hit.